The current market expects delivery of fault-free parts to the user. Delivery of fault-free parts can only be assured if the test procedures catch all possible faults. Part of a known test procedure for microcomputers is the running of a test program, a sequence of microcomputer instructions called test patterns, which exercise and monitor all elements of the microcomputer's operation.
The starting point for test pattern development is the generation of a long sequence of instructions which will, in the judgment of a designer, thoroughly and completely exercise all functions of the microcomputer to be tested. Next, these initial test patterns are fault graded by any of several commonly available logic simulators. The result of fault grading is a list of undetected possible faults. This list usually contains many thousand fault names, wherein a fault name is a node name and an associated fault condition such as "stuck high" or "stuck low". Each fault name in this list must be analyzed and a sequence of instructions devised which will detect the fault condition.
The task of developing test patterns of the highest quality is a tedious and time-consuming task frequently requiring complex and ingenious instruction sequences in order to exercise and monitor deeply embedded circuitry. Modifications to the microcomputer design and its testing procedures are needed to make the development of test patterns more straightforward and considerably less time consuming for the test engineer.
FIG. 1 is a block diagram of a known decoder 1. Address signals are provided to address lines A1-An which are each coupled to one of inverters I1-In and to a transistor array 2. Thus, address signals and inverted address signals are provided to the transistor array 2. The transistor array 2 is an array of transistors and may be implemented as one of a variety of well-known arrays. The decoder 1 also has output lines S1-Sm from the transistor array 2. The logic value of each of address signals A1-An make predetermined transistors in transistor array 2 turn on and turn off so that one of the output lines S1-Sm becomes a logic high level.
It is important that transistors in the transistor array 2 correctly turn on and turn off in response to the address signals to produce a decoded signal on output lines S1-Sm. In the manufacture of transistor array 2 it is important to produce a one hundred percent functional transistor array. To manually check or verify functionality of a large transistor array is time consuming and very costly.